.PHONY: imgs run all sim clean latest $(IMG)
TOP = top
WORK_DIR  = $(shell pwd)
# BUILD_DIR = $(shell if [ ! -d $(WORK_DIR)/build ]; then mkdir $(WORK_DIR)/build; fi;)
BUILD_DIR = $(WORK_DIR)/build
ifneq ($(wildcard ./csrc/filelist_$(TOP).mk),)
include ./csrc/filelist_$(TOP).mk
endif
VSRC += $(WORK_DIR)/vsrc/core.v
VSRC += $(WORK_DIR)/vsrc/Hazards_ctrl.v
VSRC += $(WORK_DIR)/vsrc/Reg.v
VSRC += $(WORK_DIR)/vsrc/toy_cpu.v
VSRC += $(WORK_DIR)/vsrc/Cache/*.v 
VSRC += $(WORK_DIR)/vsrc/Fetch/*.v 
VSRC += $(WORK_DIR)/vsrc/Decode/*.v 
VSRC += $(WORK_DIR)/vsrc/Execute/*.v 
VSRC += $(WORK_DIR)/vsrc/Memory/*.v 
VSRC += $(WORK_DIR)/vsrc/Writeback/*.v 
VSRC += $(WORK_DIR)/vsrc/Peripher/*.v 

VSRC += $(WORK_DIR)/vsrc/sim/$(TOP).v $(WORK_DIR)/vsrc/soc_unused/*.v
CSRC += $(WORK_DIR)/csrc/sim_$(TOP).cpp
INCLUDES += -CFLAGS -I$(WORK_DIR)/csrc

LDFLAGS =  -LDFLAGS $(NEMU_HOME)/build/riscv64-nemu-interpreter-so
LDFLAGS += -LDFLAGS -lreadline
LDFLAGS += -LDFLAGS -lLLVM-14
LDFLAGS += -LDFLAGS -lSDL2

LLVM_CFLAGS = -CFLAGS -I/usr/lib/llvm-14/include -CFLAGS -std=c++14   -CFLAGS -fno-exceptions -CFLAGS -D_GNU_SOURCE -CFLAGS -D__STDC_CONSTANT_MACROS -CFLAGS -D__STDC_FORMAT_MACROS -CFLAGS -D__STDC_LIMIT_MACROS
LLVM_CFLAGS += -CFLAGS -fPIE

TEST_BIN_DIR = $(NEMU_HOME)/../am-kernels/tests/cpu-tests/build
TEST_DIR = $(NEMU_HOME)/../am-kernels/tests/cpu-tests/tests
IMG = $(basename $(notdir $(shell find $(TEST_DIR)/. -name "*.c")))


TEST_SUFFIX = -riscv64-nemu.bin

COLOR_RED   = \033[1;31m
COLOR_GREEN = \033[1;32m
COLOR_NONE  = \033[0m


RESULT = .result
$(shell > $(RESULT))

run: Makefile.$(IMG)

imgs: $(addprefix Makefile., $(IMG))
	@echo ""

$(IMG): %: Makefile.%

Makefile.%: $(TEST_DIR)/%.c latest
	@echo "$*:"
	@if $(BUILD_DIR)/model_$(TOP)/V$(TOP) $(ARG)  $(TEST_BIN_DIR)/$*$(TEST_SUFFIX)  ; then \
		printf "[%14s] $(COLOR_GREEN)PASS!$(COLOR_NONE)\n" $* >> $(RESULT); \
	else \
		printf "[%14s] $(COLOR_RED)FAIL!$(COLOR_NONE)\n" $* >> $(RESULT); \
	fi
	-@rm -f Makefile.$*
	
gen:
	@$(shell if [ ! -d $(BUILD_DIR) ]; then mkdir $(BUILD_DIR); fi;)
	@verilator --cc   $(VSRC) $(CSRC)  $(INCLUDES) -CFLAGS -DMODEL_$(TOP) $(LLVM_CFLAGS) $(LDFLAGS)  --top $(TOP) --build -Mdir $(BUILD_DIR)/model_$(TOP) --exe -j 16 $(ARGS)
	
# @make -C  $(BUILD_DIR)/model_$(TOP) -f V$(TOP).mk
# @if $(BUILD_DIR)/model_$(TOP)/V$(TOP) %; then \
# 	printf "[%14s] $(COLOR_GREEN)PASS!$(COLOR_NONE)\n" $* >> $(RESULT); \
# else \
# 	printf "[%14s] $(COLOR_RED)FAIL!$(COLOR_NONE)\n" $* >> $(RESULT); \
# fi
# @make latest
allbin:gen
#	@verilator --cc   $(VSRC) $(CSRC)  $(INCLUDES) -CFLAGS -DMODEL_$(TOP) $(LLVM_CFLAGS) $(LDFLAGS)  --top $(TOP) --build -Mdir $(BUILD_DIR)/model_$(TOP) --exe  $(ARGS)
	@make simbin
simbin: compile imgs
	@cat $(RESULT)
	@rm $(RESULT)

compile:
	$(call git_commit, "sim RTL")
	@make -s -C  $(BUILD_DIR)/model_$(TOP) -f V$(TOP).mk

clean:
	@rm -r $(BUILD_DIR)
all:gen
#	@verilator --cc   $(VSRC) $(CSRC)  $(INCLUDES) -CFLAGS -DMODEL_$(TOP) $(LLVM_CFLAGS) $(LDFLAGS)  --top $(TOP) --build -Mdir $(BUILD_DIR)/model_$(TOP) --exe $(ARGS)
	@make sim
sim: compile
	$(BUILD_DIR)/model_$(TOP)/V$(TOP) $(ARG) $(IMG)

MERGE_VSRC += $(WORK_DIR)/vsrc/core.v
MERGE_VSRC += $(WORK_DIR)/vsrc/Hazards_ctrl.v
MERGE_VSRC += $(WORK_DIR)/vsrc/Reg.v
MERGE_VSRC += $(WORK_DIR)/vsrc/toy_cpu.v
MERGE_VSRC += $(WORK_DIR)/vsrc/Cache/*.v 
MERGE_VSRC += $(WORK_DIR)/vsrc/Fetch/*.v 
MERGE_VSRC += $(WORK_DIR)/vsrc/Decode/*.v 
MERGE_VSRC += $(WORK_DIR)/vsrc/Execute/*.v 
MERGE_VSRC += $(WORK_DIR)/vsrc/Memory/*.v 
MERGE_VSRC += $(WORK_DIR)/vsrc/Writeback/*.v 
MERGE_VSRC += $(WORK_DIR)/vsrc/Peripher/*.v 

merge: $(MERGE_VSRC)
	@cat $(MERGE_VSRC) > ysyx_22050920.v
	@python ./format.py
latest:

include ../Makefile
